Browse Standards
IEEE Guide for Investigating and Analyzing Power Cable, Joint, and Termination Failures on Systems Rated 5 kV Through 46 kV
This guide applies to the process of investigating, evaluating, and analyzing field failures. This guide covers the overall format for failure analysis and subsequent guides will specifically address cables, joints, terminations and separab...
IEEE Standard for the Universal Test Interface Framework and Pin Configuration for Portable/Benchtop Test Requirements Utilizing IEEE 1505(TM) Receiver Fixture Interface Standard
Portable/benchtop test equipment applications are supported in this document by defining a mass interconnection scheme and pin configuration based upon IEEE Std 1505(TM)-2010 and IEEE Std 1505.1(TM)-2015. Particular emphasis has been placed...
IEEE Standard for the Common Test Interface Pin Map Configuration for High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505 - Redline
An extension to the IEEE 1505TM receiver fixture interface (RFI) standard specification is provided in this standard. Particular emphasis is placed on defining within the IEEE 1505 RFI standard a more specific set of performance requirement...
IEC/IEEE International standard for receiver fixture interface
A mechanical and electrical specification for implementing a common interoperable mechanical quick-disconnect interconnect system for use by industry for interfacing large numbers of electrical signals (digital, analog, RF, power, etc.) is ...
IEEE Recommended Practice for Radar Cross-Section Test Procedures
The process of the measurement of the radar cross section of objects using a test range is described in this recommended practice. The term radar cross section (RCS) is defined, and the characteristics of different types of test ranges are ...
IEEE Standard Testability Method for Embedded Core-based Integrated Circuits - Redline
A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrato...
IEEE Standard Interface for Hardware Description Models of Electronic Components
The standard interface for hardware description models of electronic components is defined. The primary audiences of this standard are model developers and implementers of software supporting this interface.
IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards - Part 3: Standard Delay Format (SDF) for the Electronic Design Process
The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be ma...
IEEE Standard for a Chip and Module Interconnect Bus: SBus
An input/output expansion bus with a 32- or 64-bit width is described in this standard. The SBus is designed for systems requiring a small number of expansion ports. SBus Cards may be connected to a standard SBus Connector mounted on the mo...
IEEE Guide for Evaluation of Solvents Used for Cleaning Electrical Cables and Accessories
Test procedures for evaluating the physical characteristics of cable-cleaning solvents and their compatibility with extruded dielectric cable components and cable accessories (joints and terminations) are provided in this guide. Compatibili...