Browse Standards
IEEE Standard for Learning Technology-Learning Technology Systems Architecture (LTSA)
IEEE Standard for Digital Test Interchange Format (DTIF)
The information content and the data formats for the interchange of digital test program data between digital automated test program generators (DATPGs) and automatic test equipment (ATE) for board-level printed circuit assemblies are defin...
IEEE Guide for Selecting and Using Reliability Predictions Based on IEEE 1413
A framework for reliability prediction procedures for electronic equipment at all levels is provided in this guide .
IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis
Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that...
IEEE Unapproved IEEE Draft Standard for Verilog? Hardware Description Language (Revision of 1364-1995) Replaced by Approved IEEE Draft
IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 body. An annex is provided to suggest ways in which one might use this package.
IEC/IEEE International Standard - Guide for incorporating human reliability analysis into probabilistic risk assessments for nuclear power generating stations and other nuclear facilities
A structured framework for the incorporation of human reliability analysis (HRA) into probabilistic risk assessments (PRAs) is provided in this guide. To enhance the analysis of human/system interactions in PRAs, to help ensure reproducible...
IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for A...
IEEE Standard VHDL Synthesis Packages
The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation...
IEEE Standard VHDL Mathematical Packages
The MATH_REAL package declaration, the MATH_COMPLEX package declaration, and the semantics of the standard mathematical definition and conventional meaning of the functions that are part of this standard are provided. Ways for users to impl...