Parallel-Processing-Based Digital Predistortion Architecture and FPGA Implementation for Wide-band 5G Transmitters

This paper presents a bandwidth-scalable and hardware-efficient parallel-processing-based D PD architecture for wide-band 5G transmitters. By computing multiple data samples at each clock cycle in parallel, the proposed DPD architecture extends the bandwidth of a conventional serial DPD architecture, as limited by the maximum FPGA clock rate, to a much higher rate that is proportional to the number of parallel data paths. With a cross-bar structure devised to reroute the intermediate computation results between the parallel data paths, it allows advanced DPD model with memory and cross-terms to be constructed efficiently. F or proof-of-concept, the pruned Complexity-Reduced-Volterra (CRV) DPD with four parallel data paths has been implemented using an Xilinx Ultrascale+ FPGA to achieve a total linearization bandwidth of 1.25 GHz. Subsequently, a 28 GHz power amplifier modulated with 400 MHz QAM64 signals has been successfully linearized in the proposed DPD system in real-time.