3D SRAM Design & Optimization with Open Source Memory Compiler

As the prevalence of AI and big data computing, memory is becoming a performance bottleneck. 3D memory stacking is proposed to deal with this problem. However, memory physical design is a labor-intensive procedure. To the best of our knowledge, there is no existing design automation tool supporting 3D memory design. This paper extends the functionality of the open-source 2D memory compiler OpenRAM to support automatically layout generation and power and timing analyses for 3D SRAM. Based on user inputs (such as the memory capacity, tier number, and technology library), our work demonstrates the automatic generation of multi-tier 3D SRAM layouts, with NCSU 45nm FreePDK3D technology library. For memory design with 32bit word width and capacities of 1kb, 2kb, 4kb, 8kb, and 16kb, the area of the generated two-tier 3D SRAM is, on average, 17% smaller than that of 2D SRAM. For the 64bit word width case, the area of the 3D SRAM is, on average, 38% smaller than that of 2D SRAM. However, for the same capacity, the average power consumption of the two-tier 3D SRAM is 1.6% higher than that of 2D SRAM, while the read time is 15% higher than that of 2D SRAM, which shows that 3D integration may not be suitable for small capacity memory in terms of power and performance due to large TSV parasitics..