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Saman Adham
Also published under:S. M. I. Adham, S. Adham, Saman M. I. Adham
Affiliation
TSMC, Austin, TX
Topic
Power Efficiency,Stacking Process,Technology Node,Test Design,Area Overhead,Bit-width,Bitwise Operations,Bridging Mode,Business Model,CMOS Technology,Clock Cycles,Clock Frequency,Clock Period,Control Signal,Conventional Diagnosis,Cost Of Testing,Customer Demand,Data Bus,Data Capture,Data Rate,Datapath,Design Firms,Diagnosis Method,Diagnosis Of Failure,Digital Flow,Electronic Design Automation,Evaluation Phase,Failure Analysis,Fault Location,Filtering Effect,Filtering Method,Fine-tuned,Forward Error Correction,Gain Error,General Considerations,Good Integrity,Ground Plane,Half-cell,Hamming Weight,Heterogeneous Integration,Individual Channels,Inductive Load,Input Bits,Integrated Circuit Design,Internal Power,Internet Of Things,Inverter,Lack Of Accuracy,Load Data,Low-voltage Operation,
Biography
Saman Adham (M'95–SM'00) received the B.Sc. and M.Sc. degrees from the University of Baghdad, Iraq, in 1977 and 1979, respectively, and the Ph.D. from Queens University, Kingston, Ontario, Canada, in 1991, all in electrical engineering.
He is a senior manager of the ASIC design group with TSMC at the Ottawa Design Center. He has published more than 50 papers and holds more than 12 patents. He is the chair of the IEEE P1450.6.2 working standardization group.
He is a senior manager of the ASIC design group with TSMC at the Ottawa Design Center. He has published more than 50 papers and holds more than 12 patents. He is the chair of the IEEE P1450.6.2 working standardization group.