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Kerem Akarvardar
Also published under:K. Akarvardar
Affiliation
Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA
Topic
Energy Efficiency,Area Overhead,Bit-width,Circuit Design,Deep Neural Network,Input Bits,Load Data,Memory Bandwidth,Per Cycle,Scalable Technology,Technology Node,Voltage Scaling,Accuracy Loss,Accuracy Of Network,Analog Domain,Big Data,Bitwise Operations,Clock Cycles,Clock Period,Computational Load,Convolutional Layers,Data-intensive Computing,Deep Neural Network Layers,Digital Domain,Digital Flow,Encoding Strategies,Energy Domain,Even Number,Final Sum,Flexible Support,Floating-point Operations,Foundational Technologies,Gain Error,Graphics Processing Unit,Ground Plane,Hardware Overhead,Hardware Technology,Horizontal Plane,ImageNet,Input Vector,Integrated Circuit Design,Internet Of Things,Inverter,Key Items,Key Performance Metrics,Lack Of Accuracy,Low Voltage,Low-voltage Operation,Mapping Strategy,Maximum Operating Frequency,
Biography
Kerem Akarvardar (Senior Member, IEEE) received the Ph.D. degree in electrical engineering from Grenoble Institute of Technology, Saint-Martin-d’Hères, France.
He is a Senior Program Manager with TSMC Corporate Research, San Jose, CA, USA. He focuses on technologies to support AI hardware and their co-optimization with design, architecture, and algorithms. Prior to TSMC, he was with GlobalFoundries as an Assignee to IBM Semiconductor at Albany Nanotech, Albany, NY, USA.
He is a Senior Program Manager with TSMC Corporate Research, San Jose, CA, USA. He focuses on technologies to support AI hardware and their co-optimization with design, architecture, and algorithms. Prior to TSMC, he was with GlobalFoundries as an Assignee to IBM Semiconductor at Albany Nanotech, Albany, NY, USA.