Stefano Ambrogio

Also published under:S. Ambrogio

Affiliation

IBM Research, San Jose, CA, USA

Topic

Deep Neural Network,Hardware Accelerators,Kirchhoff’s Current Law,Neural Network,Non-volatile Memory,Ohm’s Law,Synaptic Weights,Analog-to-digital Converter,Landing Pad,Long Short-term Memory,Memory Devices,Mesh Network,Parallelization,Processing Unit,Transformer,Aggregate Score,Benchmark,Bitstream,Code Generation,Code Snippets,Coding Efficiency,Compensation Technique,Crossbar Array,Current Law,Digital Architecture,Effects Of Drift,Electronic Design Automation,Evaluation Framework,Grain Boundaries,Graphics Processing Unit,Heterogeneous Architecture,High Energy Efficiency,Inference Accuracy,Language Model,Large Language Models,Large Volumes Of Data,Multiple Benchmarks,Non-volatile Memory Devices,Off-chip Memory,Performance Gap,Problem Description,Problem Statement,Recurrent Network,Resistive Random Access Memory,Similar Queries,Syntactic,Test Bench,Testing Framework,Weight Matrix,Wide Range Of Models,

Biography

Stefano Ambrogio (S’14) received the M.S. (cum laude) degree and the Ph.D. degree in electrical engineering from the Politecnico di Milano, Milan, Italy, in 2012 and 2016, respectively.
His current research interests include electrical characterization, modeling, and neuromorphic applications of resistive switching devices.