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John Barth
Also published under:J. E. Barth, J. Barth
Affiliation
IBM Corporation Systems and Technology Group, Burlington, VT
Topic
Deep Trench,3D Integration,High Performance,Reactive Ion Etching,Silicon-on-insulator,3D Aggregates,3D Design,3D Stacks,3D Technology,Access Time,Area Overhead,Array Of Devices,Beginning Of Cycle,Capacity Density,Charge Pump,Conventional 2D,Coupling Mechanism,Data Cache,Decoupling Capacitor,Design Tool,Dimensions Of Integration,Doping Concentration,Equivalent Series Resistance,Fabrication Process,Front Side,High Voltage,High-performance Applications,High-performance Processors,High-voltage Generator,Implementation Considerations,Integration Scheme,Inverter,L2 Cache,Large Cages,Large Swings,Low Voltage,Low-temperature Oxidation,Metal Layer,NAND Gate,Noise Tolerance,Outer Electrode,Parasite Extracts,Performance Metrics,Positive Feedback,Prototype,Random Access,Random Access Memory,Remote Memory,Sense Amplifier,Series Resistance,
Biography
John Barth (SM'08) received the B.S.E.E. degree from Northeastern University, Boston, MA, in 1987, and the M.S.E.E. degree from National Technological University (NTU), Fort Collins, CO, in 1992. During his B.S. degree work, he was employed at the Timeplex Development Laboratory in Rochelle Park, NJ, from 1984 to 1985, where he wrote data communications and network monitoring software. He also cooped at the IBM Development Laboratory in Essex Junction, VT, in 1986, where he was involved in the design and characterization of the 1 Mb DRAM product.
He works on embedded DRAM, macro architecture and core design for IBM Systems and Technology Group, Burlington, VT, and is currently developing SOI embedded DRAM macros for high-performance microprocessor cache applications. After completing his BS degree, he returned to the IBM Development Laboratory in Essex Junction, VT, during which time he was involved the design of a 16 Mb DRAM product featuring embedded ECC and SRAM cache. Following this, he was involved the array design for the 16/18 Mb DRAM products and in 1994, started work on wide I/O, high-performance DRAM macros for embedded general-purpose ASIC applications. Utilization of these macros expanded into network switching, standalone caches for P5 and P6 microprocessors and embedded caches for the Blue Gene/L supercomputer. He holds 25 U.S. patents with eight pending and has coauthored nine IEEE papers.
Mr. Barth was co-recipient of the ISSCC Beatrice Award for Editorial Excellence in 2002 for a 144 Mb DRAM targeted for standalone SRAM cache replacement. From 2002 through 2007, he was a member of the IEEE ISSCC Memory Subcommittee responsible for conference organization and paper selection. His paper, “A 50 ns 16-Mb DRAM with 10 ns Data Rate and On-Chip ECC,” received the IEEE Journal of Solid-State Circuits 1989–1990 Best Paper Award.
He works on embedded DRAM, macro architecture and core design for IBM Systems and Technology Group, Burlington, VT, and is currently developing SOI embedded DRAM macros for high-performance microprocessor cache applications. After completing his BS degree, he returned to the IBM Development Laboratory in Essex Junction, VT, during which time he was involved the design of a 16 Mb DRAM product featuring embedded ECC and SRAM cache. Following this, he was involved the array design for the 16/18 Mb DRAM products and in 1994, started work on wide I/O, high-performance DRAM macros for embedded general-purpose ASIC applications. Utilization of these macros expanded into network switching, standalone caches for P5 and P6 microprocessors and embedded caches for the Blue Gene/L supercomputer. He holds 25 U.S. patents with eight pending and has coauthored nine IEEE papers.
Mr. Barth was co-recipient of the ISSCC Beatrice Award for Editorial Excellence in 2002 for a 144 Mb DRAM targeted for standalone SRAM cache replacement. From 2002 through 2007, he was a member of the IEEE ISSCC Memory Subcommittee responsible for conference organization and paper selection. His paper, “A 50 ns 16-Mb DRAM with 10 ns Data Rate and On-Chip ECC,” received the IEEE Journal of Solid-State Circuits 1989–1990 Best Paper Award.