E. Adler

Affiliation

Semiconductor Research and Development Center, IBM Microelectronics, VT, USA

Topic

Gate Oxide,Rapid Thermal Annealing,Gate Electrode,Levels Of Metals,Oxide Thickness,Plasma-enhanced Chemical Vapor Deposition,Secondary Ion Mass Spectrometry,Selective Etching,Silicon Nitride,Threshold Voltage,Threshold Voltage Shift,polySia,2D Model,Active Area Of The Device,Active Region,Aspect Ratio,Bias Conditions,Boron Concentration,Buried Layer,CMOS Logic,CMOS Technology,Cell Size,Cell Structure,Channel Length,Chemical Vapor Deposition,Chromatography,Complete Process,DRAM Technology,Design Points,Device Reliability,Device Thickness,Drain Current,Early Stages Of Development,Effect Of Fluorination,Electrical Engineering,Electrostatic Discharge,End Of Process,Etching,Field-effect Transistors,Flicker Noise,Fluorinated,Fluorine Content,Ground Rules,Improvement In Stability,Increase In Complexity,Increase In Thickness,Interface Increases,Interface Trap,Ionizing Radiation,Junction Structure,

Biography

Eric Adler received the B.S. degree in physics from the City College of New York, in 1959, and the Ph.D. degree in physics from Columbia University, New York, in 1965.
After one year as a Post Doctoral Fellow at the IBM Watson Laboratory, and two years as Assistant Professor of physics at the City College of New York, he joined the IBM Corporation in 1968, where he is currently a Senior Engineer. He has worked in the field of silicon device reliability, DRAM and logic technology and device design, design and characterization of devices, and passive components for analog and RF applications. He retired from IBM in 2002.