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D. Bensahel
Also published under:Daniel-Camille Bensahel, Daniel Bensahel
Affiliation
Central Research and Development, STMicroelectronics, Crolles, France
Topic
Data Retention,Impedance,Amorphous Phase,Amorphous Solid,Non-volatile Memory,SET Pulse,Band Gap,Carbon Doping,Crystallization Temperature,Direct Gap,Memory Technologies,Phase Change Materials,Program Characteristics,Resistance Values,Rutherford Backscattering,Silicon-on-insulator,Two-dimensional Crystals,Activation Energy,Active Devices,Arrhenius Equation,Automotive Products,Band Structure,Brillouin Zone,Carbon Impurities,Carrier Density,Carrier Mobility,Chemical Vapor Deposition,Condensation Method,Conduction Band,Consumption Of Products,Density Of States,Electrical Performance,Epitaxial,Function Of Temperature,Gate Stack,Ge Enrichment,Ge Lasers,Hexagonal Lattice,High Conductivity,High Temperature,Higher Crystallization Temperature,In-plane Strain,Material Characterization,Memory Cells,Optical Gain,Optical Measurements,Optical Reflectance,Periodic Lattice,Photoluminescence,Photonic Crystal Cavities,
Biography
Daniel-Camille Bensahel received the Ph.D. degree for work on II–VI compounds from the Université Scientifique et Médicale de Grenoble, Grenoble, France.
He joined France Telecom R&D, where for 20 years he developed laser annealing, RTP, and SiGe processes for CMOS and BiCMOS. Since 2000, he has been with STMicroelectronics as Advanced Front-End Materials Manager, where he studies the advanced basic modules of the FEOL for 45 nm and below nodes: substrates including Si-Ge-C, gate stack with high k/Metal, and USJ and contacts.
He joined France Telecom R&D, where for 20 years he developed laser annealing, RTP, and SiGe processes for CMOS and BiCMOS. Since 2000, he has been with STMicroelectronics as Advanced Front-End Materials Manager, where he studies the advanced basic modules of the FEOL for 45 nm and below nodes: substrates including Si-Ge-C, gate stack with high k/Metal, and USJ and contacts.