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Rachata Ausavarungnirun
Affiliation
Sirindhorn International Thai-German Graduate School, King Mongkut’s University of Technology North Bangkok, Bangkok, Thailand
Topic
Load Data,Neighboring Vertices,Parallelization,Address Translation,Analog Computing,Division Operation,Energy Efficiency,Graph Algorithms,Graph Data,Hardware Accelerators,Hash Function,Improve Energy Efficiency,Neighbor List,PageRank Algorithm,Random Access,Resistive Random Access Memory,Serialized,Source Vertex,Sparsity,Vertex Values,Virtual Memory,Aachen University,Adaptive Algorithm,Address Mapping,Address Space,Analog-to-digital Converter,Area Overhead,Average Degree,Baseline System,Caching,Center For Control,Compressed Format,Computational Expense,Computational Graph,Context Switching,Conventional Function,Conventional Memory,Convolutional Neural Network,Crossbar Array,Current Node,Current Sequencing Technologies,Current Step,DNA Base Pairs,DNA Molecules,Data Structure,Delta Values,Design Points,Digital Circuits,Dijkstra’s Algorithm,End Location,
Biography
Rachata Ausavarungnirun (Member, IEEE) received the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 2017.
He is a Lecturer with the Sirindhorn International Thai-German Graduate School of Engineering, King Mongkut’s University of Technology North Bangkok, Bangkok, Thailand. His research spans multiple topics across computer architecture and system software with emphasis on GPU architecture, heterogeneous CPU–GPU architecture, management of GPUs in the cloud, memory subsystems, memory management, processing-in-memory, nonvolatile memory, network-on-chip, and accelerator designs.
He is a Lecturer with the Sirindhorn International Thai-German Graduate School of Engineering, King Mongkut’s University of Technology North Bangkok, Bangkok, Thailand. His research spans multiple topics across computer architecture and system software with emphasis on GPU architecture, heterogeneous CPU–GPU architecture, management of GPUs in the cloud, memory subsystems, memory management, processing-in-memory, nonvolatile memory, network-on-chip, and accelerator designs.