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Rahul Bera
Affiliation
ETH Zürich
Topic
Physical Address,Baseline System,Power Overhead,Access Latency,Caching,Data Cache,L2 Cache,Performance Benefits,Address Translation,Area Overhead,Context Switching,Data Block,Hash Function,Key Observation,Key Takeaway,Load Data,Mapping Strategy,Memory Address,Memory Hierarchy,Physical Memory,Replacement Policy,Virtual Memory,Access Patterns,Additional Bits,Address Mapping,Address Space,Amount Of Shift,Bounding Box,Cache Hit,Candidates For Replacement,Code Examples,Computational Performance,Computing Units,Conventional Function,Conventional Memory,Core Processes,Critical Path,Data Resources,Data Structure,Datapath,Direct Access,Double-precision Floating-point,Dynamic Optimization,Dynamic Power Consumption,Energy Consumption,Execution Environment,Fast Translation,Flexible Segments,Free Space,Function Calls,
Biography
Rahul Bera received the master’s degree in computer science from the Indian Institute of Technology Kanpur, in 2017. He is currently pursuing the Ph.D. degree with ETH Zürich, Switzerland. He has worked with AMD and Intel Labs, India. His research interests include the broad areas of memory hierarchy design and applied machine learning in computer architecture.