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Nilmini Abeyratne
Affiliation
University of Michigan, Ann Arbor, MI, USA
Intel Corporation, Santa Clara, CA, USA
Intel Corporation, Santa Clara, CA, USA
Topic
Average Latency,Low Latency,Memory Control,Network Latency,Network-on-chip,Virtual Channel,Activation Energy,Active Part,Area Overhead,Asymmetric Design,Bandwidth Allocation,Bandwidth Usage,Bank Group,Bank Structure,Bit Error Rate,Cache Misses,Channel Bandwidth,Cluster Nodes,Communication Performance,Continuous Flow,Conventional Design,Efficient Repair,Energy Conservation,Energy Consumption,Forward Error Correction,Global Communication,High Bandwidth,High Latency,High Power,High Throughput,Hop Count,Increase In Power,Injection Rate,Input Port,Latency Constraints,Local Communication,Low Complexity,Mapping Strategy,Memory Cells,Memory Technologies,Mesh Network,Most Significant Bit,Multi-core,Multi-hop Networks,Network Delay,Network Diameter,Network Load,Network Throughput,Non-volatile Memory,Number Of Wires,
Biography
Nilmini Abeyratne received the PhD degree in computer science and engineering from the University of Michigan, Ann Arbor, in 2013. She is a performance architect with Intel Corporation. Her particular area of research is computer architecture as it applies to high performance computing, supercomputers, memory, and interconnects.