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Jung Ho Ahn
Also published under:J. Ahn
Affiliation
Seoul National University, Seoul, South Korea
Topic
Memory Bandwidth,Datapath,L2 Cache,Memory Capacity,On-chip Memory,Attention Layer,Computing Units,Data Reuse,High Bandwidth,Memory Footprint,Off-chip Memory,Adjacent Rows,Area Overhead,Attention Mechanism,Automorphism,Batch Size,Encrypted Data,Fully-connected Layer,Input Sequence,Input Tokens,Matrix Multiplication,Matrix Size,Memory Control,Memory System,Performance Degradation,Plaintext,Single Kernel,Tile Size,Transformer Model,Access Latency,Aggregation Operators,Aggregation Phase,Bandwidth Requirements,Baseline System,Bit Error,Bit Error Rate,Caching,Computational Capabilities,Convolutional Neural Network,Counter Value,Crater Lake,Device Memory,Energy Efficiency,Error Characteristics,Fast Fourier Transform,Feature Matrix,Fully Homomorphic Encryption,Function Matrix,GB Memory,Half-cell,
Biography
Jung Ho Ahn (Senior Member, IEEE) received the BS degree in electrical engineering from Seoul National University, and the MS and PhD degrees in electrical engineering from Stanford University, Stanford, CA. He is currently a professor with the Graduate School of Convergence Science and Technology, Seoul National University, Seoul, South Korea, where he leads the Scalable Computer Architecture Laboratory. He is interested in bridging the gap between the performance demand of emerging applications and the performance potential of modern, and future massively parallel systems.