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Sanguhn Cha
Also published under:Sang-Uhn Cha, Sang-uhn Cha
Affiliation
Samsung Electronics, Hwaseong, Korea
Topic
Area Overhead,Bank Group,Datapath,High Speed,Parity-check,10-nm Process,Adaptive Scheme,Advanced Driver Assistance Systems,Artificial Intelligence Technology,Augmented Reality System,Bit Error,Bit Error Rate,Chromatography,Clock Cycles,Code Blocks,Cosmic Rays,Current Control,Cut-and-paste,DRAM Device,DRAM Process,Data Bus,Data Cache,Data Retention,Data Transfer,Decoding Time,Deep Learning,Dual Camera,Error Detection,Extensive Measurements,Fabrication Technology,Forward Error Correction,High Bandwidth,High-frequency Data,High-speed Data,Image Recognition,Increase In Capacity,Internal Operations,Large Capacity,Memory Capacity,Memory Control,Memory System,Operating Frequency,Performance Degradation,Power Recovery,Rapid Development,Read Operation,Sense Amplifier,Stable Performance,Stable Recovery,Storage Capacity,
Biography
Sanguhn Cha was born in Busan, Korea, in 1982. He received the B.S., M.S., and the Ph.D. degrees in electrical and electronic engineering from Yonsei University, Seoul, Korea, in 2005, 2007, and 2013, respectively.
Since 2013, he has been with Samsung Electronics, Hwaseong, Korea, involved in DRAM design team. His research interests include low-voltage memory circuits and technology, error correction codes, and evolvable hardware design.
Since 2013, he has been with Samsung Electronics, Hwaseong, Korea, involved in DRAM design team. His research interests include low-voltage memory circuits and technology, error correction codes, and evolvable hardware design.