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Young Yong Byun
Also published under:Young-Yong Byun
Affiliation
Memory Division, Samsung Electronics, Hwaseong, South Korea
Topic
Bank Group,Bit Error,Bit Error Rate,Design Techniques,High Bandwidth,Memory Capacity,Operating Frequency,Parity-check,Read Operation,Stable Performance,Test Pattern,Voltage Drop,Active Switches,Artificial Intelligence Technology,Block Diagram,Chip Size,Codeword,Control Logic,Cyclic Redundancy Check,Data Window,Deep Learning,Error Control,Error Detection,High Capacity,High Frequency Modes,High Speed,High-frequency Data,Host Side,Image Recognition,Increase In Capacity,Large Capacity,Low-frequency Domain,Low-frequency Modes,Manufacturing Defects,Memory System,Pattern Generator,Practical Techniques,Rapid Development,Successful Deployment,Synergetic,Testing Coverage,Time Window,Timing Diagram,Transaction Data,
Biography
Young Yong Byun received the B.S. and M.S. degrees from Dongguk University, Seoul, South Korea, in 2002 and 2004, respectively.
He joined the Memory Division, Samsung Electronics, Hwaseong, South Korea, in 2004, where he has been involved in DDR3 and DDR4 DRAM, and is currently engaged in high-bandwidth memory-2 (HBM2), HBM2E, and HBM3.
He joined the Memory Division, Samsung Electronics, Hwaseong, South Korea, in 2004, where he has been involved in DDR3 and DDR4 DRAM, and is currently engaged in high-bandwidth memory-2 (HBM2), HBM2E, and HBM3.