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Sungoh Ahn
Also published under:S. Ahn
Affiliation
Memory Division, DRAM Design Team, Samsung Electronics, Hwaseong, South Korea
Topic
Bit Error,Bit Error Rate,High Bandwidth,Memory Capacity,Operating Frequency,Parity-check,Voltage Drop,Artificial Intelligence Technology,Bank Group,Block Diagram,Chip Size,Codeword,Comparable Yields,Control Logic,Data Window,Deep Learning,Design Techniques,External Resistance,High Bandwidth Memory,High Capacity,High Frequency Modes,High Speed,High-frequency Data,Image Recognition,Increase In Capacity,Large Capacity,Low-frequency Modes,Manufacturing Defects,Measurement Of Leakage,Memory System,Phase-locked Loop,Rapid Development,Read Operation,Serialized,Stable Performance,Successful Deployment,Synergetic,Test Pattern,Time Window,Absolute Difference,Acceptable Test,Channel Flow,Coil System,Fabrication Process,Flow Distribution,Flow Test,Insulation System,Kapton Tape,Mm In Direction,Peak Flux,
Biography
Sungoh Ahn received the B.S. degree from Kyung Hee University, Yongin, South Korea, in 2010.
In 2010, he joined the Memory Division, Samsung Electronics, Hwaseong, South Korea, where he has been involved in DRAM I/O circuit design. His research interests include 3-D-DRAM circuit design and technology, low-power and high-speed I/O circuit design, and signal integrity issues in high-speed and wide I/O channel.
In 2010, he joined the Memory Division, Samsung Electronics, Hwaseong, South Korea, where he has been involved in DRAM I/O circuit design. His research interests include 3-D-DRAM circuit design and technology, low-power and high-speed I/O circuit design, and signal integrity issues in high-speed and wide I/O channel.