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Haerang Choi
Affiliation
SK hynix Inc., South Korea
Topic
Activation Function,Load Data,Matrix Multiplication,Software Stack,Computation Time,Internal Circuit,Leaky ReLU,Linear Interpolation,Lookup Table,SK Hynix,System Architecture,System-level Performance,Word Line,Application Of Deep Learning,Attention Mechanism,Circuit Area,Current Consumption,Deep Neural Network,Design Choices,Domain-specific Memory,Feed-forward Network,Floating-point Operations,GPU Card,Hyperbolic Tangent,Inference Cost,Inference Performance,Inference System,Integer Part,Key Metrics,Large Language Models,Matrix Multiplication Operation,Matrix Production,Matrix-vector Product,Memory Processes,Mobile System,Multicast,Multilayer Perceptron,Negative Input,Normal Operation,Performance Bottleneck,Performance In Phase,Performance Measures,Performance Metrics,Phase Response,Power Consumption,Previous Results,Processing Unit,Prototype,Recurrent Neural Network,Scalable Architecture,
Biography
Haerang Choi received the B.S. and M.S. degrees from Hanyang University, Seoul, South Korea, in 2005 and 2007, respectively, and the Ph.D. degree in computer science and engineering from Seoul National University, Seoul, in 2021.
From 2007 to 2016, he designs and develops dynamic random access memory (DRAM) circuits with SK Hynix Inc. Since 2021, he has been developing in-memory computation architecture with SK Hynix Inc. His current research interests include memory sub-systems and memory-domain architecture for neural networks and its accelerator.
From 2007 to 2016, he designs and develops dynamic random access memory (DRAM) circuits with SK Hynix Inc. Since 2021, he has been developing in-memory computation architecture with SK Hynix Inc. His current research interests include memory sub-systems and memory-domain architecture for neural networks and its accelerator.