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Junhyun Chun
Also published under:Jun Hyun Chun, Jun-Hyun Chun, J. Chun
Affiliation
SK hynix inc.
Topic
Activation Function,Clock Generator,Matrix Multiplication,Phase-locked Loop,Power Consumption,Clock Signal,Clocking Architecture,Computation Time,Eye Diagrams,High Bandwidth,Internal Circuit,Layout Optimization,Leaky ReLU,Linear Interpolation,Load Data,Lookup Table,Phase Alignment,Phase Mismatch,Read Operation,Software Stack,System Architecture,System-level Performance,Word Line,Application Of Deep Learning,Automatic Generation,Bit Error Rate,CMOS Process,Channel Loss,Circuit Area,Clock Frequency,Clock Phase,Control Delay,Control Sequence,Conventional Structure,Critical Path,Current Consumption,Dead Zone,Deep Neural Network,Delay Line,Delay Unit,Delay-locked Loop,Design Methodology,Device Structure,Differential Pair,Digital Block,Digital Circuits,Domain-specific Memory,Floating-point Operations,Frequency Range,Heavy Load,
Biography
Junhyun Chun received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, South Korea, in 1992.
In 1992, he joined LG Semiconductor, Cheongju, South Korea, where he was engaged in the dynamic random access memory (DRAM) design. Since 2000, he has been with SK Hynix, Icheon, South Korea, where he has been engaged in various high-speed, high-density DRAM design and ultra-low-power mobile DRAM design. He is currently in charge of the SoC Division as the Senior Vice bbreak President.
In 1992, he joined LG Semiconductor, Cheongju, South Korea, where he was engaged in the dynamic random access memory (DRAM) design. Since 2000, he has been with SK Hynix, Icheon, South Korea, where he has been engaged in various high-speed, high-density DRAM design and ultra-low-power mobile DRAM design. He is currently in charge of the SoC Division as the Senior Vice bbreak President.