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A. Athmanathan
Also published under:Aravinthan Athmanathan
Affiliation
IBM Research, Rüschlikon, Switzerland
Topic
Non-volatile Memory,Bit Error Rate,Data Readout,Data Retention,Impedance,Memory Technologies,Phase Change Materials,Activation Energy,Adjacent Levels,Amorphous Solid,Current Reference,Effects Of Drift,Endurance Cycling,High Resistance,High Resistance State,I-V Curves,Intermediate Levels,Levels Of Resistance,Low Resistance,Low Resistance State,Readout Scheme,Reliable Storage,Threshold Switching,Additional Heat,Adjacent States,Ambient Temperature Range,Ambient Temperature Variation,Bias Current,Bias Voltage,Big Data Applications,Binary Search,Bit Error Rate Performance,CMOS Technology,Codeword,Conductive Medium,Constant Current,Current Flow,Current Fluctuations,Current Mirror,Data Storage,Detection Efficiency,Detection Threshold,Device Efficiency,Device Operation,Digital Control,Distribution Of Levels,Drift Coefficient,Dynamic Range,Effective Resolution,Elevated Temperature,
Biography
Aravinthan Athmanathan received the M.Sc. degree in electrical engineering from the Swiss Federal Institute of Technology, Lausanne (EPFL), Switzerland, in 2011. He joined IBM Research-Zurich, Ruschlikon, Switzerland, in 2010, where he is currently pursuing his doctoral thesis in collaboration with the Microelectronics Systems Laboratory (LSM) at EPFL. His doctoral thesis is focused on modeling and reliability aspects of multilevel-cell phase-change memory.
He has been involved in IC design of READ/WRITE architectures for phase-change memory. His research interests include readout metrics for emerging non-volatile memory technologies, device characterization and reliability analysis of exploratory memory arrays and finite-element method based modeling of thermal and electrical transport in memory devices.
He has been involved in IC design of READ/WRITE architectures for phase-change memory. His research interests include readout metrics for emerging non-volatile memory technologies, device characterization and reliability analysis of exploratory memory arrays and finite-element method based modeling of thermal and electrical transport in memory devices.