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Junho Cheon
Also published under:Jun-Ho Cheon
Affiliation
DRAM Development, SK hynix Inc., Icheon, Republic of Korea
Topic
Abrupt Switching,Al2O3 Layer,Aspect Ratio,Binary Code,Bit Error,Bit Error Rate,Bottom Layer,CMOS Process,Chip Size,Crossbar Array,Current Amplifier,Current Mirror,Current Source,Device Variation,Digital Code,Edge Devices,Endurance Cycling,Ferroelectric,High Aspect Ratio,Hold Time,Hysteresis Curves,Improve Energy Efficiency,Inference Accuracy,Input Current,Interpolation Technique,Inverter,Ion Diffusion,Loop Bandwidth,Low Voltage,Low-power Sensors,Low-voltage Operation,Migration Of Atoms,Multilevel Cell,Negative Bias,Neural Network,Noise Contribution,Open Voltage,Output Code,Oxygen Ions,Parasitic Capacitance,Peak Current,Peripheral Circuits,Power Consumption,Properties Of Devices,Prototype,Readout Circuit,Remnant Polarization,Residual Generator,Resistive Switching,Root Mean Square Values,
Biography
Jun-Ho Cheon received the B.S., M.S., and Ph.D. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 2002, 2004, and 2009, respectively.
In 2012, he joined the Next Generation Memory design team, SK hynix Inc., Icheon, Korea, where he is currently a Senior Research Engineer. His research interest is on the design of a read and write circuitry for multi-level next-generation memory including phase-change memory.
In 2012, he joined the Next Generation Memory design team, SK hynix Inc., Icheon, Korea, where he is currently a Senior Research Engineer. His research interest is on the design of a read and write circuitry for multi-level next-generation memory including phase-change memory.