Sandeep Bagchi

Gate Dielectric,Silicide,Carrier Mobility,Gate Length,Silicon-on-insulator,Bright-field Images,Channel FETs,Charge Trapping,Compressive Strain,Crystallinity,Current Id,Device Architecture,Device Fabrication,Device Performance,Device Simulation,Differences In Thickness,Doping Profile,Double-gate,Drain Current,Electric Field Strength,Electrostatic Potential,Electrostatic Potential Distribution,Extensive Regions,Field-effect Transistors,Focused Ion Beam Milling,Gate Leakage,Gate Oxide,Gate Region,Good Channel,HfO2 Gate Insulator,High Levels Of Strain,Hologram,Horizontal Channel,Isothermal,Lateral Field,Metal Gate,Mobility Enhancement,Off-axis Electron Holography,Oxide Thickness,Planar Devices,Potential Profile,Protective Layer,Reduction In Leakage,SRAM Bitcell,Sample Preparation,Sample Preparation Method,Sample Thickness,Sidewall,Thermal Budget,Thin Body,