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Chaitali Chakrabarti
Also published under:C. Chakrabarti, Chaitaili Chakrabarti
Affiliation
Arizona State University
Topic
Application Programming Interface,Accuracy Loss,Adversarial Attacks,Adversary Model,Applicability Domain,Application Tasks,Baseline Methods,Binary Activation,Binary Format,Binary Model,Binary Network,Binary Neural Networks,Breadth-first Search,CNN Model,Call Graph,Channel Size,Channel Width,Clock Frequency,Communication Patterns,Complete Network,Compression Scheme,Control Flow Graph,Convolutional Layers,Critical Edge,Deep Neural Network,Deep Neural Network Architecture,Deep Neural Network Model,Digital Signal Processing,Dijkstra’s Algorithm,Direct Object,Directed Graph,Domain-specific Languages,Emulation Platform,Energy Efficiency,Energy Meter,Error Handling,External Dependence,Fast Fourier Transform,File System,Flash Memory,Flow Control,Formal Verification,Function Calls,Gain In Accuracy,Graphics Processing Unit,Growth Stages,Hardware Accelerators,Hardware Architecture,Heterogeneous Architecture,Image Processing,
Biography
Chaitali Chakrabarti (Fellow, IEEE) received the B.Tech. degree in electronics and electrical communication engineering from IIT Kharagpur, Kharagpur, India, in 1984 and the Ph.D. degree in electrical engineering from the University of Maryland, College Park, MD, USA, in 1990.
She is currently a Professor with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA. Her research interests include very-large-scale integration (VLSI) algorithm-architecture co-design of signal processing and communication systems and all aspects of low-power embedded systems design.
She is currently a Professor with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA. Her research interests include very-large-scale integration (VLSI) algorithm-architecture co-design of signal processing and communication systems and all aspects of low-power embedded systems design.