Haitham Eissa

Also published under:Haitham M. Eissa, H. M. Eissa, H. Eissa

Affiliation

Mentor Graphics Corporation, Cairo, Egypt

Topic

Circuit Design,Effects Of Stress,Physical Design,Physical Layout,Stress Parameters,Analog Circuits,Catastrophic Failure,Design Manufacturing,Device Behavior,Device Dimensions,Device Parameters,Electric Simulation,Electrical Detection,Lookup Table,Parallel Design,Current Mirror,Design Constraints,Design Purposes,Design Specifications,Differential Pair,Electrical Behavior,Electrical Circuit,Layout Design,Physical Problems,Proximity Effect,SPICE Simulations,Saturation Current,Semiconductor Industry,Transistor Channel,Translational Level,Analog Devices,Basic Building Blocks,Circuit Performance,Circuit Simulation,Critical Path,Design Flow,Design Methodology,Design Parameters,Device Group,Differential Signal,Electrical Characteristics,Engineering Design,Extensive Simulations,Finite Impulse Response Filter,Full Chip Design,Impact Of Knowledge,Integrated Circuit Design,Inverter,Laboratory Measurements,Lithography Process,

Biography

Haitham Eissa received the B.Sc. degree in electronics and communication engineering and the M.Sc. degree in electronics engineering from the Faculty of Engineering, Ain Shams University, Cairo, Egypt, in 1997 and 2004, respectively, where he is currently pursuing the Ph.D. degree in integrated circuits, mainly in layout effects on circuit design performance.
He is a Technical Marketing Leader with the Calibre Design Solutions Division, Mentor Graphics, Cairo. He is involved in research to define EDA software requirements to serve the continuous needs of the electronics circuit designs environment. He was a Consultant Engineer for major electronics companies in the field of electronics design, such as IBM, Alcatel, and others. He has authored or co-authored several publications on analog and mixed signal design flow, integrated circuit, and layout physical verification.