Topic
- Computing and Processing
- Components, Circuits, Devices and Systems
- Communication, Networking and Broadcast Technologies
- Power, Energy and Industry Applications
- Signal Processing and Analysis
- Robotics and Control Systems
- General Topics for Engineers
- Fields, Waves and Electromagnetics
- Engineered Materials, Dielectrics and Plasmas
- Bioengineering
- Transportation
- Photonics and Electrooptics
- Engineering Profession
- Aerospace
- Geoscience
- Nuclear Engineering
- Career Development
- Emerging Technologies
- Telecommunications
- English for Technical Professionals
D. Acharyya
Also published under:Dhruva Acharyya, D. J. Acharyya, Dhruva J. Acharyya
Affiliation
AdvanTest, Inc., USA
Topic
Low Leakage,Physical Unclonable Functions,Power Grid,Calibration Process,High Leakage,Non-volatile Memory,Pairing,Probability Of Failure,Test Chip,Boxplots,Current Source,Hardware Experiments,Logic Blocks,Multiple Ports,Offset Voltage,Path Delay,Percentage Change,Port-a-cath,Random Pairs,Relative Phase,Resistant Varieties,State Machine,Technology Node,Test Sequences,Thermoelectric Coolers,Thresholding Technique,Valid Path,Variable Levels,Variation In Profiles,Voltage Drop,2D Plane,Advanced Capabilities,Agilent Technologies,Application Programming Interface,Authentication Scheme,Bar Height,Base Case,Bleeding,Bottom Of Page,Calibration Dataset,Calibration Test,Capacitive Coupling,Changes In Values,Chip Design,Chip Fabrication,Clock Generator,Collision Probability,Column Plots,Computed Pearson Correlations,Consecutive Pulses,
Biography
Jim Plusquellic holds a degree in computer science from the University of Pittsburgh, PA, in 1997. He is currently an Associate Professor in ECE at the University of New Mexico. His research interests include security and trust in IC hardware, silicon validation, design for manufacturability and delay test methods. He is a member of the IEEE and the IEEE Computer Society's Golden Core.