Topic
- Computing and Processing
- Components, Circuits, Devices and Systems
- Communication, Networking and Broadcast Technologies
- Power, Energy and Industry Applications
- Signal Processing and Analysis
- Robotics and Control Systems
- General Topics for Engineers
- Fields, Waves and Electromagnetics
- Engineered Materials, Dielectrics and Plasmas
- Bioengineering
- Transportation
- Photonics and Electrooptics
- Engineering Profession
- Aerospace
- Geoscience
- Nuclear Engineering
- Career Development
- Emerging Technologies
- Telecommunications
- English for Technical Professionals
Krste Asanović
Also published under:K. Asanovic, Krste Asanovic, Krste Asanovíc, K. Asanović
Affiliation
UC Berkeley
Topic
Deep Neural Network,Area Overhead,Memory System,Microarchitecture,Physical Design,AlexNet,Application Of Deep Neural Networks,Deadlock,Deep Neural Network Model,Deployment Scenarios,Geometric Mean,L2 Cache,Load Data,Memory Resources,Quality Of Service Requirements,Scalable,Service Quality,Shared Memory,SqueezeNet,System Throughput,Task Queue,16-nm FinFET,Adaptive Management,Allocation Mechanism,Amazon Web Services,Backward Compatibility,Baseline Solution,Bitstream,Cache Hit,Chain Length,Clock Frequency,Cluster Core,Combinational Logic,Communication Latency,Communication Protocol,Convolutional Layers,Data Cache,Deep Neural Network Architecture,Deep Neural Network Layers,Design Flow,Design Methodology,Design Space,Design Space Exploration,Digital Circuits,Disc Images,Distributed Architecture,Dynamic Memory,Energy Efficiency,Functional Unit,Golden Gate,
Biography
Krste Asanović is currently a Professor at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. Asanovic received the Ph.D. degree in computer science from the University of California, Berkeley. He is a Fellow of IEEE and the Association for Computing Machinery. Contact him at [email protected].