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Akram Ben Ahmed
Affiliation
The Digital Architecture Research Center, National Institute of Advanced Industrial Sciences and Technology, 2-3-26 Aomi, Koto-ku, Tokyo, Japan
Topic
Edge Computing,Frame Interval,Frame Size,Highest Classification,Power Consumption,Scheduling Algorithm,Switching Network,Time-sensitive Networking,Transmission Time,3D Mesh,3D Technology,Academic Work,Accuracy Drop,Active Switches,Area Overhead,Arrival Rate,Arrival Time,Artificial Neural Network,Bit Error Rate,Blue Box,Commercial Off-the-shelf,Confidence Level,Conventional Architecture,Defect Clusters,Defect Layer,Defect Rate,Destination Port,Deterministic,Distribution Of Clusters,Electromigration,Energy Consumption,Flow Algorithm,Flow Path,Forward Error Correction,Hardware Architecture,Hardware Complexity,Hardware Implementation,Hardware Level,High Temperature,Hotspot Areas,IEEE Standard,Increase In Latency,Input Port,Largest Standard Deviation,Latency Measures,Leaky Integrate-and-fire,Least Significant Bit,Lookup Table,Low Power Consumption,Lowest Weight,
Biography
AKRAM BEN AHMED received the MSE and PhD degrees in computer science and engineering from the University of Aizu, Japan, in 2012 and 2015, respectively. He is currently a postdoctoral researcher in the Department of Information and Computer Science, Keio University, Japan. His current research interests include on-chip interconnection networks, reliable and fault-tolerant systems, and ultra-low-power embedded real-time systems. He is a member of the IEEE.