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K. Albin
Affiliation
Motorola, Inc., Austin, TX, USA
Topic
Constraint Satisfaction Problem,Gene Vector,Input Variables,State Variables,Original Constraints,Boolean Constraints,Boolean Function,Connective,Formal Verification,Functional Verification,Number Of Input Variables,Random Generation,Random Vector,Reduction In Time,State Machine,Stimulus Generation,Syntactic,Test Bench,Time And Space,Boolean Variable,Clock Cycles,Complete Extraction,Disjunction,Free Variables,Function Of Variables,Functional Decomposition,General Solution,Groups Of Variables,Hardware Constraints,Industrial Settings,Input Bias,Joining Tree,Normal Form,Priority Level,Random Simulations,Random Walk,Set Of Rules,State Design,Verification Method,Arithmetic Operations,Commutative Diagram,Datapath,Decision Problem,Deep Pipeline,Degree Of Automation,Design Center,Design Objectives,Educational Settings,Engineering Design,Essential Step,
Biography
Ken Albin received the B.S.E.E. and M.S.E.E. degrees from Kansas State University, Manhattan, in 1981 and 1984, respectively.
He is a Staff Member in Motorola SPS's SoC/Advanced Tools Area, focusing on formal verification tools and design methodology. He is the Current Chairman of the SPS Functional Verification Methodology Development Council. Previously, he spent five years as a Verification Manager of Motorola's Embedded Platform Solutions Group, focusing on the integration of new tools and methodology. Prior to Motorola, he performed formal verification research at Computational Logic Inc., and worked in a processor-design group at Rockwell-Collins, Cedar Rapids, IA.
He is a Staff Member in Motorola SPS's SoC/Advanced Tools Area, focusing on formal verification tools and design methodology. He is the Current Chairman of the SPS Functional Verification Methodology Development Council. Previously, he spent five years as a Verification Manager of Motorola's Embedded Platform Solutions Group, focusing on the integration of new tools and methodology. Prior to Motorola, he performed formal verification research at Computational Logic Inc., and worked in a processor-design group at Rockwell-Collins, Cedar Rapids, IA.