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L. Altimime
Also published under:Laith Altimime
Affiliation
imec, Leuven, Belgium
Topic
Resistive Random Access Memory,Oxygen Vacancies,Resistive Switching,Atomic Layer Deposition,Bipolar Switching,Conduction Band,Conductive,Cycling,Electrical Characteristics,Electrode,I-V Curves,Pulse Amplitude,SET Pulse,Top Electrode,Activation Energy,Capacitor Structure,Capping Layer,Cell Size,Constriction,Discrete Energy Levels,Discrete Levels,Dynamic Balance,Energy Barrier,Energy Levels,High Resistance State,Impact Ionization,Non-volatile Memory,Oxide Film,Oxide Thickness,Properties Of Filaments,Pulse Width,Quantum Mechanical Model,Quantum Mechanics,Random Access Memory,Reactive Ion Etching,Reset Process,Switching Mechanism,Technology Node,Work Function,3D Simulation,Ab Initio,Ab Initio Simulation,Al2O3 Layer,Amount Of Oxygen Vacancies,Anatase,Anodic Oxidation,Array Size,As-deposited Films,Asymmetric Distribution,Back-end-of-line,
Biography
Laith Altimime was born in 1962. After receiving the Honours degree in 1989 in applied physics and semiconductors electronics from Heriot Watt University in Edinburgh (Scotland), he joined NEC Semiconductors—UK as a device yield and integration engineer. He also worked in NEC-Japan and NEC-China.
In 2002, he moved to Germany as head of fab engineering in a new foundry startup, Communicant. He then joined Infineon in 2004 as Project Manager for nonvolatile memory technologies development (CBRAM and MRAM) at Altis Semiconductors (France).
In 2002, he moved to Germany as head of fab engineering in a new foundry startup, Communicant. He then joined Infineon in 2004 as Project Manager for nonvolatile memory technologies development (CBRAM and MRAM) at Altis Semiconductors (France).