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A. Bette
Affiliation
Infineon, Munich, Germany
Topic
Current Mirror,Sense Amplifier,Voltage Difference,Word Line,Block Level,Current Sink,Load Current,Magnetic Interference,Mirroring,Peripheral Circuits,Physical Orientation,Random Access Memory,Single Array,Access Time,Circuit Design,Current Reference,Current Source,Cycle Time,Entire Chip,Error Floor,Established Platform,Flash Memory,Free Layer,Gate Capacitance,Inductive Load,Loading Device,Low Resistance State,Magnetoresistance,Memory Array,Memory Technologies,Operator Of Order,Pulse Width,Read Operation,Read Voltage,Reading Performance,Reference System,Scanning Electron Microscopy,Symmetric Design,Test Chip,Test Circuit,Tunnel Junction,Turnitin,Resistance State,
Biography
Alexander Bette received the Dipl.-Ing. degree in electrical engineering from the Technical University Munich, Germany, in 1996.
He joined Siemens Semiconductor (now Infineon Technologies) as a member of the Product Engineering group of the memory products division. He was responsible for production test development and for test and characterization of current and new DRAM memory designs. He also supported the worldwide production and test facilities of Infineon, including on-location support through travels and assignments. In May 2001, he joined the MRAM Development Alliance of Infineon Technologies and IBM Corporation. After the end of that alliance, he continues as a member of the Infineon MRAM design and test team in Burlington, VT, responsible for design characterization and test.
He joined Siemens Semiconductor (now Infineon Technologies) as a member of the Product Engineering group of the memory products division. He was responsible for production test development and for test and characterization of current and new DRAM memory designs. He also supported the worldwide production and test facilities of Infineon, including on-location support through travels and assignments. In May 2001, he joined the MRAM Development Alliance of Infineon Technologies and IBM Corporation. After the end of that alliance, he continues as a member of the Infineon MRAM design and test team in Burlington, VT, responsible for design characterization and test.