Topic
- Computing and Processing
- Components, Circuits, Devices and Systems
- Communication, Networking and Broadcast Technologies
- Power, Energy and Industry Applications
- Signal Processing and Analysis
- Robotics and Control Systems
- General Topics for Engineers
- Fields, Waves and Electromagnetics
- Engineered Materials, Dielectrics and Plasmas
- Bioengineering
- Transportation
- Photonics and Electrooptics
- Engineering Profession
- Aerospace
- Geoscience
- Nuclear Engineering
- Career Development
- Emerging Technologies
- Telecommunications
- English for Technical Professionals
Christian Arndt
Also published under:C. Arndt
Affiliation
Qimonda Dresden GmbH and Company OHG, Neubiberg, Germany
Topic
Current Mirror,Sense Amplifier,Word Line,Block Level,Current Sink,Load Current,Low Resistance State,Magnetic Interference,Mirroring,Peripheral Circuits,Physical Orientation,Random Access Memory,Single Array,Voltage Difference,Access Time,Carbon Allotropes,Carbon Nanotubes,Circuit Design,Conductance States,Critical Current,Critical Current Density,Current Pulse,Current Reference,Cycle Time,Entire Chip,Error Floor,Free Layer,Graphene,High Conductivity,High Resistance State,High-speed Switching,Low Resistance,Memory Cells,Memory Effect,Memory Technologies,Non-volatile Memory,Pulse Width,Read Operation,Reading Performance,Reference System,Resistance State,Resistive Memory,Scanning Electron Microscopy,Short Pulse,Single-walled Carbon Nanotubes,Test Chip,Test Circuit,Thin Filaments,Tunnel Junction,Turnitin,
Biography
Christian Arndt received the title Associate Engineer from the Siemens Technik Akademie, Munich, Germany, in 1996.
During eight years with Siemens Semiconductor Division and Infineon Technologies, he was engaged in the development of several DRAM (4Mb–512Mb), RAMBUS, FeRAM, and MRAM physical designs. He is currently a Senior Engineer and coordinates the physical design activities of next-generation DRAM in Munich.
During eight years with Siemens Semiconductor Division and Infineon Technologies, he was engaged in the development of several DRAM (4Mb–512Mb), RAMBUS, FeRAM, and MRAM physical designs. He is currently a Senior Engineer and coordinates the physical design activities of next-generation DRAM in Munich.