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Han-Seob Cha
Affiliation
R&D center, MagnaChip Semiconductor, Choongbook, Korea
Topic
Sheet Resistance,Thermal Stability,CMOS Technology,High-temperature Annealing,Ionizing Radiation,Low Resistance,Low Sheet Resistance,Nanoengineering,Gate Length,Rapid Thermal Annealing,Silicide,X-ray Photoelectron Spectroscopy,Active Region,Advantages Of Low Cost,Annealing Temperature,Arsenic Concentrations,Atomic Ratio,Average Roughness,Average Surface Roughness,Capping Layer,Critical Conditions,Cross-sectional TEM,Device Performance,Dislocation Loops,Doping Type,Etching Rate,Function Of Width,Gate Dielectric,Gate Oxide,Ge Concentration,High Temperature,Hot Electrons,Impedance,Improve Device Performance,Increase In Resistance,Junction Region,Junction Temperature,Lattice Strain,Leakage Current Increases,Linewidth,N2 Atmosphere,Nanoscale,Nanoscale CMOS,Nicotine,On-off Ratio,Plasma Immersion Ion Implantation,Processing Window,Rapid Thermal,Rapid Thermal Processing,Scanning Probe Microscopy,
Biography
Han-seob Cha was born in Korea in 1972. He received the B.S. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1994 and the M.S. degree in materials science and engineering from Pohang University of Science and Technology, Pohang, Korea, in 1996.
In 1996, he joined the System IC Research and Development Center, Hynix Semiconductor Inc., Cheongju, Korea, where he was engaged in development of CMOS logic technology and SoC devices. From 1998 to 1999, he worked on wafer level reliability of MOSFET. Since 2000 he has worked on developing 0.15 and 0.13 $\mu$ m technology, and is now developing 90 nm technology. His research interests include strained silicon transistor and SiGe HBT processes.
In 1996, he joined the System IC Research and Development Center, Hynix Semiconductor Inc., Cheongju, Korea, where he was engaged in development of CMOS logic technology and SoC devices. From 1998 to 1999, he worked on wafer level reliability of MOSFET. Since 2000 he has worked on developing 0.15 and 0.13 $\mu$ m technology, and is now developing 90 nm technology. His research interests include strained silicon transistor and SiGe HBT processes.