Imran Hafeez Abbassi

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Affiliation

College of Aeronautical Engineering, National University of Sciences and Technology, Islamabad, Pakistan

Topic

Dynamic Power,Functional Verification,Gate Capacitance,Model Checking,NAND Gate,Propagation Delay,Security Vulnerabilities,Side-channel,State-space Model,Total Capacitance,Types Of Attacks,Vulnerability Assessment,Above-mentioned Analysis,Active Switches,Area Overhead,Area Threshold,Basic Circuit,Benchmark,Bootstrap Resampling,Circuit Area,Circuit Model,Circuit Performance,Circuit Power,Circuit Power Consumption,Clock Cycles,Complex Circuits,Computational Complexity,Convolutional Codes,Convolutional Encoder,Cost-effective Solution,Critical Path,Custom Instruction,Data Cache,Decoding Algorithm,Decoding Process,Design Constraints,Detection Techniques,Digital Signal Processing,Digital Television,Dynamic Power Consumption,Early Design Stages,Efficient Implementation,Electronic Design Automation,Execution Stage,Footprint Area,Formal Framework,Formal Verification,Forward Error Correction,Function Tests,Functional Characterization,

Biography

Imran Hafeez Abbassi is currently an Associate Professor with CAE, NUST since April 2019. His research interests include hardware security, cryptography, formal verification, machine learning, and embedded system design.
Dr. Abbassi is also an Awardee of the Ph.D. Scholarship from Higher Education Commission, Pakistan.