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Levent Aksoy
Also published under:L. Aksoy
Affiliation
Department of Computer Systems, Tallinn University of Technology, Tallinn, Estonia
Topic
Hardware Complexity,Secret Key,Corruption,Input Patterns,Primary Output,Threat Model,Boolean Function,Delay Constraint,Input Values,Key Input,Logic Locking,Primary Input,Reverse Engineering,Area Gain,Boolean Algebra,Boolean Logic,Clock Cycles,Critical Path,Critical Signaling,Electronic Design Automation,Elliptic Curve,Exhaustive Search,Filter Design,Final Equation,Finite Impulse Response Filter,Graph-based Algorithm,Input Variables,Key Values,Large Constant,Minimum Delay,Original Design,Output Filter,Synthesis Tool,Value Of Bit,Architectural Design,Area Mm2,Attack Results,Average Power Consumption,Binary Search,CMOS Process,CMOS Technology,Cadence,Channel Length,Channel Width,Commercial Tools,Compressor,Constant Set,Control Input,Conventional Implementation,Correct Technique,
Biography
Levent Aksoy (Member, IEEE) received the Ph.D. degree in electronics engineering from Istanbul Technical University (ITU), Istanbul, Turkey, in 2009.
He worked as a Researcher at ITU and INESC-ID, Lisbon, Portugal. He also worked at Dialog Semiconductor, Istanbul, as a Senior Digital Design Engineer. He is currently a Postdoctoral Researcher at the Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia. His research interests include hardware security and CAD for VLSI circuits with an emphasis on solving electronic design automation (EDA) problems using satisfiability (SAT) models and optimization techniques.
He worked as a Researcher at ITU and INESC-ID, Lisbon, Portugal. He also worked at Dialog Semiconductor, Istanbul, as a Senior Digital Design Engineer. He is currently a Postdoctoral Researcher at the Centre for Hardware Security, Tallinn University of Technology (TalTech), Tallinn, Estonia. His research interests include hardware security and CAD for VLSI circuits with an emphasis on solving electronic design automation (EDA) problems using satisfiability (SAT) models and optimization techniques.