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Sangun Choi
Also published under:
Affiliation
School of Electrical Engineering, Korea University, Seoul, Republic of Korea
Topic
Access Latency,Access Patterns,Buffer Size,CNN Model,Counter Value,Deep Neural Network,Deep Neural Network Layers,Deep Neural Network Model,Design Space Exploration,Energy Consumption,Energy Efficiency,Global Access,Hardware Configuration,Hardware Overhead,Hardware Resources,High Energy Efficiency,Inference Time,Input Matrix,Large Matrix,Load Data,Off-chip Memory,Output Buffer,Performance Degradation,Scheduling Techniques,Short Time Window,Systolic Array,Systolic Dimensions,Two-level Structure,Vision Transformer,Weight Matrix,
Biography
Sangun Choi received the B.S. degree in railroad electrical and electronics engineering from Korea National University of Transportation, in 2021, and the M.S. degree in electrical and computer engineering from Sungkyunkwan University, in 2024. He is currently pursuing the Ph.D. degree in electrical engineering with Korea University. His research interest includes energy-efficient neural network accelerator architectures.