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Jaume Abella
Also published under:J. Abella
Affiliation
Barcelona Supercomputing Center (BSC), Barcelona, Spain
Topic
Safety-critical,L2 Cache,Object Detection,Convolutional Neural Network,Advanced Driver Assistance Systems,Assignable Cause,Autonomous Vehicles,Avionics,Energy Efficiency,Graphics Processing Unit,Instruction Set Architecture,Low Precision,Memory Control,Multi-core,Neural Network,Power Consumption,Arbitration,Area Overhead,Autonomic System,Benchmark,Bounding Box,Deep Neural Network,Deterministic,Development Process,Electronic Design Automation,Forward Error Correction,Hardware Accelerators,Matrix Multiplication,Memory Hierarchy,Memory System,Misprediction,Open-source,Operating System,Physical Design,Random Access Memory,Safety Standards,Stochastic Nature,Test Scenarios,Vehicle Safety,Verification And Validation,3D Architecture,3D Integration,AI Models,AI-based Systems,Acceptable Threshold,Access Latency,Additional Bits,Alternative Hypothesis,Amount Of Shift,Analysis Tasks,
Biography
Jaume Abella (Member, IEEE) received the Ph.D. degree from UPC, Spain, in 2005. He joined Barcelona Supercomputing Center (BSC), in 2009 where he co-leads the CAOS group. Formerly, he worked as Senior Researcher with the Intel Corporation (2005–2009). His research focuses on safety critical systems for the automotive, avionics and space domains among others, including hardware and software safety support for RISC-V architectures, and AI-based autonomous system design, implementation, validation and certification. Other topics of interest are microprocessor reliability and testing, use of commercial HPC MPSoCs in safety-relevant systems, and technology transfer to industry. He is the Principal Investigator of the project Horizon Europe SAFEXPLAIN, and is or has been BSC's PI for several other HE, H2020, Chips JU, KDT JU, ECSEL JU, and ARTEMIS JU projects. He has 14 patents and over 250 publications in top peer-reviewed conferences and journals, and has co-advised 30 Ph.D. and master students.