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Franck Arnaud
Also published under:F. Arnaud
Affiliation
STMicroelectronics, Crolles, France
Topic
Back-end-of-line,High Performance,Low Voltage,Parasitic Capacitance,28-nm FDSOI,3D Integration,Activation Energy,Active Material,Arrhenius Plot,Back End,Bit Error Rate,CMOS Process,Carrier Mobility,Channel Area,Charge Pump,Color Code,Cycling,Design Techniques,Device Performance,Device Structure,Effective Channel,Effective Width,End Of Line,Field-effect Transistors,Figure Of Merit,Final Channel,Final Region,Final Space,Forward Error Correction,Gate Capacitance,Gate Oxide,Ge Concentration,Ground Plane,High Dynamic Range,High Dynamic Range Pixel,Higher Threshold,Internet Of Things,Inverter,Left Picture,Low Consumption,Low Leakage,Low Power,Metal Lines,Metal Oxide,Microcontroller Unit,Mobility Degradation,Net Polarization,Non-volatile Memory,Onset Of Crystallization,Part Of The Paper,
Biography
Franck Arnaud joined STMicroelectronics in 1995 after his graduation with a Master degree in the field of electronics from the Superior School of Electricity, Paris, France. He started the ramp-up of 0.35 $\mu$ m CMOS technology as FEOL engineer. In 2008, he spent two and half years in the Fishkill area working in ISDA semi-conductor alliance led by IBM as 32/28 nm device manager. He moved back to Crolles site in France in 2010 where he took the responsibility of the 28 nm program development for both bulk and FDSOI technologies as director.